---

Scalable Sub-micron Design Rules

The following rules are taken from the MOSIS webpage:

http://www.mosis.org/New/Technical/Designrules/dr-scmos72.html

Please note that the following rules are SUB-MICRON enhanced lambda based rules. Only rules relevant to the HP-CMOS14tb technology are presented here. In addition to the lambda rules, the micron rules for lambda=0.3u are given in an additional column. Please refer to http://www.mosis.org/New/Technical/Designrules/dr-scmos72.html for more accurate and complete information.

Layout Rules

• 1. Well
• 2. Active
• 3. Poly
• 4. Select
• 5. Poly Contact
• 6. Active Contact
• 7. Metal-1
• 8. Via
• 9. Metal-2
• 14. Via2
• 15. Metal-3

1. Well

Rule	Description	Lambda	Microns
1.1	Minimum width	12	3.6u
1.2	Minimum spacing between wells at different potential	18	5.4u
1.3	Minimum spacing between wells at same potential	6	1.8u

2. Active

Rule	Description	Lambda	Microns
2.1	Minimum width	3	0.9u
2.2	Minimum spacing	3	0.9u
2.3	Source/drain active to well edge	6	1.8u
2.4	Substrate/well contact active to well edge	3	0.9u
2.5	Minimum spacing between active of different implant	0 or 4	0 or 1.2u

3. Poly

Rule	Description	Lambda	Microns
3.1	Minimum width	2	0.6u
3.2	Minimum spacing	3	0.9u
3.3	Minimum gate extension of active	2	0.6u
3.4	Minimum active extension of poly	3	0.9u
3.5	Minimum field poly to active	1	0.3u

4. Select

Rule	Description	Lambda	Microns
4.1	Minimum select spacing to channel of transistor	3	0.9u
4.2	Minimum select overlap of active	2	0.6u
4.3	Minimum select overlap of contact	1	0.3u
4.4	Minimum select width and spacing	2	0.6u

5. Poly Contact

Rule	Description	Lambda	Microns
5.1	Exact contact size	2x2	0.6u x 0.6u
5.2b	Minimum poly overlap	1	0.3u
5.3	Minumum contact spacing	3	0.9u
5.4	Minimum spacing to gate of transistor	2	0.6u
5.5b	Minimum spacing to other poly	5	1.5u
5.6b	Minimum spacing to active (single contact)	2	0.6u
5.7b	Minimum spacing to active (multiple contacts)	3	0.9u

6. Active Contact

Rule	Description	Lambda	Microns
6.1	Exact contact size	2x2	0.6u x 0.6u
6.2b	Minimum active overlap	1	0.3u
6.3	Minimum contact spacing	3	0.9u
6.4	Minimum spacing to gate of transistor	2	0.6u
6.5b	Minimum spacing to diffusion active	5	1.5u
6.6b	Minimum spacing to field poly (single contact)	2	0.6u
6.7b	Minimum spacing to field poly (multiple contacts)	3	0.9u
6.8b	Minimum spacing to poly contact	4	1.2u

7. Metal-1

Rule	Description	Lambda	Microns
7.1	Minimum width	3	0.9u
7.2a	Minimum spacing	3	0.9u
7.3	Minimum overlap of any contact	1	0.3u

8. Via

Rule	Description	Lambda	Microns
8.1	Exact size	2 x 2	0.6u x 0.6u
8.2	Minimum spacing	3	0.9u
8.3	Minimum overlap by Metal-1	1	0.3u
8.4	Minimum spacing to contact	2	0.6u

9. Metal-2

Rule	Description	Lambda	Microns
9.1	Minimum width	3	0.9u
9.2b	Minimum spacing	3	0.9u
9.3	Minimum overlap of via1	1	0.3u

14. Via2

Rule	Description	Lambda	Microns
14.1	Exact size	2 x 2	0.6u x 0.6u
14.2	Minimum spacing	3	0.9u
14.3	Minimum overlap by Metal-2	1	0.3u
14.4	Minimum spacing Via-1	2	0.6u

15. Metal-3

Rule	Description	Lambda	Microns
15.1	Minimum width	5	1.5u
15.2	Minimum spacing	3	0.9u
15.3	Minimum overlap of Via-2	2	0.6u

a production of

Cadence is a trademark of Cadence Design Systems, Inc., 555 River Oaks Parkway, San Jose, CA 95134.
Please read this DISCLAIMER

KGF 11/7/1998