The PMOS transistor was placed within the n-well, this well also has to be biased with the VDD potential. THis will be done with an n-type substrate contact.
We can follow the same steps that we did for the p substrate contact, but we will try to introduce another method. Almost all of the interlayer connections are already available as instances in your design library. We used the metal-poly contact instance while connecting the input. Similar instances also exist for the substrate connections.
1. From the menu Create select option Instance
( Create --> Instance )
This will pop-up the instance options menu.
You'll have to provide a cell name and library here. It may be the case that you already know the cell name and cell view, but in this case it is better to Browse in your library to find the appropriate cell.
This is essentially the same library browser that you access when you start Cadence Design Tools. It lets you choose the library, cell and cell view, your selection will be transferred to the Instance options menu.
The N-substrate contact is named NTAP, and only has a symbolic view.
2. Move the instance to the desired location.
Once you have selected the instance, the cursor will show a ghost image representing the instance, and you'll be able to move the instance to the desired location:
3. Place the instance.
Once satisfied, you can click to place the instance. You'll remain in the instance mode after you have placed the instance, press "ESC" to go back to selection mode again. Note that in this example, the n-well contact has been placed right on top of the n-well boundary, which will obviously generate a rul eviolation. the n-well is simply not wide enough to accomodate both the PMOS transistor and rge contact. This will have to be dealt with in the next step.
4. Make the power connection.
The instance will not automatically connect itself to the power supply rail. This connection has to be made by either a Metal-1 rectangle or path.
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