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In this tutorial an alternative way of drawing layouts will be introduced. This tutorial assumes that the reader is familiar with the Virtuoso layout tool and has followed the layout manual.
Since the manual creation of the physical layout is labour intensive, significant amount of work has been put into the automation of the physical layout design process. The device level placer is one of the lower-level answers. The device level placer, will read in a schematic and place all the transistors and I/O pins in the layout window. This tool will use parametric instances that will generate appropriately sized transistors.
Although the device level placer and similar contemporary tools provide some nice features, the quality of the layouts they produce are still far from hand optimized layouts.
Steps of Automatic Layout Generation
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